All, (1) FIRST EXAM The first exam of the semister will be on Thursday, 7 OCT 1999. The exam will cover chapters 1 thru 5. There will be 4 problems, with multiple parts, with a total of 100 points possible. The exam will be open book, but closed note and closed neighbor. I did not make up the exam -- the other instructor did, however I was able to complete it in about 1/2 hour. Therefore, I expect that you all will easily be able to complete it in 1 hour, 15 minutes. The regular exam problems will be very much like the homework. In addition, there will be an as yet undetermined amount of extra credit to help you along. In preparation for the exam, and since we are so far ahead of the other class, I will field questions on the homework and work example problems on Tuesday, 5 OCT 1999. (2) HOMEWORK ASSIGNMENT Here is your homework problem for Thursday, 7 OCT 1999. This one will make you actually think, instead of working a problem like the examples in the book. Therefore, it will be worth more points than the other homeworks. Imagine that you have just finished the design of the basic computer and the company you work at is selling them like hotcakes. However positive the initial response from customers is, they always want more (or so marketing says.) Marketing held customer feedback sessions and found that the basic computer needed a richer instruction set, especially in the memory-reference instructions. The customers want to be able to do the following: (A) Execute instructions with immediate data field. This field is 16-bits wide and is in the lower part of the instruction word. (B) Execute instructions that have both one and two operand addresses supplied. For those that have one operand address supplied, operate on the operand with the accumulator WITHOUT GOING THRU THE DATA REGISTER (this is to increase the performance of the computer.) For those that have two operand addresses supplied, use the data register to temporarily hold one of the operands, then use the DR to operate on the other operand directly from memory. (C) Execute a broader range of logic functions Your crack system engineering group has taken the customers' needs and boiled them down to the following set of requirements: (A)(B)(C) Above all mean changing the memory-reference instructions (listed in table 5-4) to be the following: Symbol Description ------ ----------- (This group performs immediate instructions) ANDI IVAL(15-0) AC <- AC and IR(15-0) ORI IVAL(15-0) AC <- AC or IR(15-0) XORI IVAL(15-0) AC <- AC xor IR(15-0) ADDI IVAL(15-0) AC <- AC + IR(15-0) SUBI IVAL(15-0) AC <- AC - IR(15-0) (This group performs two operand instructions and can use the DR) ANDD ADDR1(11-0) ADDR2(11-0) AC <- M[EA1] and M[EA2] ORD ADDR1(11-0) ADDR2(11-0) AC <- M[EA1] or M[EA2] XORD ADDR1(11-0) ADDR2(11-0) AC <- M[EA1] xor M[EA2] ADDD ADDR1(11-0) ADDR2(11-0) AC <- M[EA1] + M[EA2] SUBD ADDR1(11-0) ADDR2(11-0) AC <- M[EA1] - M[EA2] (This group performs one operand instructions and must not use the DR) AND ADDR(11-0) AC <- AC and M[EA] OR ADDR(11-0) AC <- AC or M[EA] XOR ADDR(11-0) AC <- AC xor M[EA] ADD ADDR(11-0) AC <- AC + M[EA] SUB ADDR(11-0) AC <- AC - M[EA] LDA ADDR(11-0) AC <- M[EA] LDI IVAL(15-0) AC <- IR(15-0) STA ADDR(11-0) M[EA] <- AC STI IVAL(15-0) M[EA] <- IR(15-0) BUN ADDR(11-0) PC <- EA BSA ADDR(11-0) M[EA] <- PC, PC <- EA + 1 ISZ ADDR(11-0) M[EA] <- M[EA] + 1, if ((M[EA] + 1) = 0) then PC <- PC + 1 You must still support both direct and indirect addressing. EA is the effective address, after either a direct load of AR with an address in the IR or an indirect load of AR with the contents of memory pointed to by an address in the IR. Marketing has given you only a limited amount of time and money to implement these changes, so you have to start from the current design and modify it to fit the new requirements -- do not start from scratch. Also, this machine should execute the instructions in as few clock cycles as possible, since we know that customers not only want more features, they do not want to sacrifice performance as well. None of these operations should go past sequencer count T7. Your solution should involve providing the following diagrams and tables: (A) A diagram similar to Figure 5-3, describing all of registers and memory. (B) A diagram similar to Figure 5-4, describing the bus structure and all of register and memory controls. (C) A diagram similar to Figure 5-5, describing the instruction format for ALL instruction types. Note that all the non-memory-reference instructions, even if they have the same function and the same sequence of micro-ops, may have a different format, since the size of the opcode for the memory reference instructions has changed. (D) A table similar to Table 5-2, listing ALL of the possible instructions. (E) A table similar to Table 5-4, listing the memory reference instructions, their decode and their description. (F) A table similar to Table 5-6, listing the micro-operations for the memory- reference instructions. Do not list the micro-operations for any of the other instructions or conditions, but do show how the condition check changed due to a change in the instruction format. For example, if CLA no longer has rB11 as a condition, show what it changed to. SOME HINTS and SUGGESTIONS: --------------------------- This problem is not as hard as it seems. All you are basically doing is increasing the number of opcodes for memory-reference instructions, adding a few data paths, and enhancing the ALU. You can assume that the ALU is more sophisticated than that of the basic computer, similar to the ALU at the end of chapter 4. It can perform all of the functions requested above, with the right select code. You do not have to design the ALU, just specify what it has to do. Defining a set of select codes to be sent to the ALU would be a good way of specifying its operation. Alternatively, you can describe in text. Think thru the implications of increasing the number of memory-reference instructions first. Realize that, if the opcode size changes, the instruction size will also have to change. What are the implication of that? You may not change the number of addresses in memory -- it is still 4K. However, you may increase the width of the memory. Alternatively, you may choose to implement a multiple 16-bit word instruction. Think about the implications of doing either of those things first. Which scheme has the most impact on the other instructions? Which scheme has the most impact on the width of the registers? It is easy to change the width of a register. The more you have to change the operation of the computer to keep the same function of the other instructions, the more writing and explaining you will have to do. It will probably be easiest to figure out the instruction format first. Do not make the memory or register width an odd value, like 19, 24, etc. Keep it a power of two wide (currently 16-bits). Try to keep as much of the instruction format, for the other types of instructions, the same as you can. Good luck, Mark D. Fries Lead Design Engineer / Blackbelt GE Medical Systems / Global CT Engineering Phone: 414-785-5725 FAX: 414-245-1607 Email: mark.fries@med.ge.com