| Format | Purpose | Description | Restrictions | Exceptions |
|---|---|---|---|---|
| ADD rd, rs, rt | To add 32-bit integers. If an overflow occurs, then trap. | rd = rs + rt The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result. • If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs. • If the addition does not overflow, the 32-bit result is placed into GPR rd. |
None | Integer Overflow |
| ADD.S fd, fs, ft | To add floating point values | fd = fs + ft The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. |
The fields fs, ft, and fd must specify FPRs. | Unimplemented Operation, Invalid Operation, Inexact, Overflow, Underflow |
| ADDI rt, rs, immediate | To add a constant to a 32-bit integer. If overflow occurs, then trap. | rt = rs + immediate The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result. • If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs. • If the addition does not overflow, the 32-bit result is placed into GPR rt. |
None | Integer Overflow |
| ADDIU rt, rs, immediate | To add a constant to a 32-bit integer | rt = rs + immediate The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rt. No Integer Overflow exception occurs under any circumstances. |
None | None |
| ADDU rd, rs, rt | To add 32-bit integers | rt = rs + rt The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rd. No Integer Overflow exception occurs under any circumstances. |
None | None |
| AND rd, rs, rt | To do a bitwise logical AND | rd = rs AND rt The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is placed into GPR rd. |
None | None |
| ANDI rt, rs, immediate | To do a bitwise logical AND with a constant | rt = rs AND immediate The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical AND operation. The result is placed into GPR rt. |
None | None |
| B offset | To do an unconditional branch | B offset is the assembly idiom used to denote an unconditional branch. The actual instruction is interpreted by the hardware as BEQ r0, r0, offset. An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. With the 18-bit signed instruction offset, the conditional branch range is ± 128 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range. | None | None |
| BEQ rs, rt, offset | To compare GPRs then do a PC-relative conditional branch | if (rs == rt) then goto branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs and GPR rt are equal, branch to the effective target address after the instruction in the delay slot is executed. |
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. | None |
| BGEZ rs, offset | To test a GPR then do a PC-relative conditional branch | if rs >= 0 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. |
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. | None |
| BGTZ rs, offset | To test a GPR then do a PC-relative conditional branch | if rs > 0 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed. |
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. | None |
| BLEZ rs, offset | To test a GPR then do a PC-relative conditional branch | if rs <= 0 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed. |
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. | None |
| BLTZ rs, offset | To test a GPR then do a PC-relative conditional branch | if rs < 0 then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. |
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. | >None |
| BNE rs, rt, offset | To compare GPRs then do a PC-relative conditional branch | if rs != rt then branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. |
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. | None |
| DIV rs, rt | To divide a 32-bit signed integers | (HI, LO) = rs / rt The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both operands as signed values. The 32-bit quotient is placed into special register LO and the 32-bit remainder isplaced into special register HI. No arithmetic exception occurs under any circumstances. |
If the divisor in GPR rt is zero, the arithmetic result value is UNPREDICTABLE. | None |
| DIV.S fd, fs, ft | To divide FP values | fd = fs / ft The value in FPR fs is divided by the value in FPR ft. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. |
None | Coprocessor Unusable, Reserved Instruction, Inexact, Invalid Operation, Unimplemented Operation, Division-by-zero, Overflow, Underflow |
| DIVU rs, rt | To divide a 32-bit unsigned integers | (HI, LO) = rs / rt The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both operands as unsigned values. The 32-bit quotient is placed into special register LO and the 32-bit remainder is placed into special register HI. No arithmetic exception occurs under any circumstances. |
If the divisor in GPR rt is zero, the arithmetic result value is UNPREDICTABLE. | None |
| J target | To branch within the current 256 MB-aligned region | This is a PC-region branch (not PC-relative); the effective target address is in the “current” 256 MB-aligned region. The low 28 bits of the target address is the instr_index field shifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself). Jump to the effective target address. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself. | Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. | None |
| JAL target | To execute a procedure call within the current 256 MB-aligned region | Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call. This is a PC-region branch (not PC-relative); the effective target address is in the “current” 256 MB-aligned region. The low 28 bits of the target address is the instr_index field shifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself). Jump to the effective target address. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself. | Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump. | None |
| JALR rs (rd = 31 implied) JALR rd, rs |
To execute a procedure call to an instruction address in a register | rd = return_addr, PC = rs Place the return address link in GPR rd. The return link is the address of the second instruction following the branch, where execution continues after a procedure call. |
Register specifiers rs and rd must not be equal, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by re-executing the branch when an exception occurs in the branch delay slot. The effective target address in GPR rs must be naturally-aligned. | None |
| JR rs | To execute a branch to an instruction address in a register | PC = rs Jump to the effective target address in GPR rs. Execute the instruction following the jump, in the branch delay slot, before jumping. |
The effective target address in GPR rs must be naturally-aligned. | None |
| LA rt, label | To load an address into a register | rt = address of label This is a psuedo instruction which the assembler replaces with two instructions. |
None | None |
| LB rt, offset(base) | To load a byte from memory as a signed value | rt = memory[base+offset] The contents of the 8-bit byte at the memory location specified by the effective address are fetched, sign-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address. |
None | TLB Refill, TLB Invalid, Address Error, Watch |
| LBU rt, offset(base) | To load a byte from memory as an unsigned value | rt = memory[base+offset] The contents of the 8-bit byte at the memory location specified by the effective address are fetched, zero-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address. |
None | TLB Refill, TLB Invalid, Address Error, Watch |
| LI rt, immediate | To load a constant into a register | rt = immediate This is a psuedo instruction which the assembler replaces with the addi instruction. |
None | None |
| LUI rt, immediate | To load a constant into the upper half of a word | rt = immediate || 0(16) The 16-bit immediate is shifted left 16 bits and concatenated with 16 bits of low-order zeros. The 32-bit result is placed into GPR rt. |
None | None |
| LW rt, offset(base) | To load a word from memory as a signed value | rt = memory[base+offset] The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched, sign-extended to the GPR register length if necessary, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address. |
The effective address must be naturally-aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs. | TLB Refill, TLB Invalid, Bus Error, Address Error, Watch |
| LWC1 ft, offset(base) | To load a word from memory to an FPR | ft = memory[base+offset] The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched and placed into the low word of coprocessor 1 general register ft. The 16-bit signed offset is added to the contents of GPR base to form the effective address. |
An Address Error exception occurs if EffectiveAddress1..0 != 0 (not word-aligned). | TLB Refill, TLB Invalid, Address Error, Reserved Instruction, Coprocessor Unusable, Watch |
| MFC1 rt, fs | To copy a word from an FPU (CP1) general register to a GPR | rt = fs The contents of FPR fs are loaded into general register rt. |
None | Coprocessor Unusable, Reserved Instruction |
| MFHI rd | To copy the special purpose HI register to a GPR | rd = HI The contents of special register HI are loaded into GPR rd. |
None | None |
| MFLO rd | To copy the special purpose LO register to a GPR | rd = LO The contents of special register LO are loaded into GPR rd. |
None | None |
| MOV.S fd, fs | To move an FP value between FPRs | fd = fs The value in FPR fs is placed into FPR fd. The move is non-arithmetic; it causes no IEEE 754 exceptions. |
None | None |
| MOVN rd, rs, rt | To conditionally move a GPR after testing a GPR value | if rt != 0 then rd = rs If the value in GPR rt is not equal to zero, then the contents of GPR rs are placed into GPR rd. | None | None |
| MOVZ rd, rs, rt | To conditionally move a GPR after testing a GPR value | if rt == 0 then rd = rs If the value in GPR rt is equal to zero, then the contents of GPR rs are placed into GPR rd. |
None | None |
| MTC1 rt, fs | To copy a word from a GPR to an FPU (CP1) general register | fs = rt The low word in GPR rt is placed into the low word of floating point (Coprocessor 1) general register fs. |
None | None |
| MUL rd, rs, rt | To multiply two words and write the result to a GPR. | rd = rs x rt The 32-bit word value in GPR rs is multiplied by the 32-bit value in GPR rt, treating both operands as signed values, to produce a 64-bit result. The least significant 32 bits of the product are written to GPR rd. The contents of HI and LO are UNPREDICTABLE after the operation. No arithmetic exception occurs under any circumstances. |
Note that this instruction does not provide the capability of writing the result to the HI and LO registers. | None |
| MUL.S fd, fs, ft | To multiply FP values | fd = fs x ft The value in FPR fs is multiplied by the value in FPR ft. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. MUL.PS multiplies the upper and lower halves of FPR fs and FPR ft independently, and ORs together any generated exceptional conditions. |
None | Inexact, Unimplemented Operation, Invalid Operation, Overflow, Underflow |
| MULT rs, rt | To multiply 32-bit signed integers | (HI, LO) = rs x rt The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating both operands as signed values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the high-order 32-bit word is splaced into special register HI. No arithmetic exception occurs under any circumstances. |
None | None |
| MULTU rs, rt | To multiply 32-bit unsigned integers | (HI, LO) = rs x rt The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating both operands as unsigned values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the high-order 32-bit word is placed into special register HI. No arithmetic exception occurs under any circumstances. |
None | None |
| NEG.S fd, fs | To negate an FP value | fd = -fs The value in FPR fs is negated and placed into FPR fd. The value is negated by changing the sign bit value. The operand and result are values in format fmt. NEG.PS negates the upper and lower halves of FPR fs independently, and ORs together any generated exceptional conditions. This operation is arithmetic; a NaN operand signals invalid operation. |
None | None |
| NOR rd, rs, rt | To do a bitwise logical NOT OR | rd = rs NOR rt The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical NOR operation. The result is placed into GPR rd. |
None | None |
| OR rd, rs, rt | To do a bitwise logical OR | rd = rs OR rt The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical OR operation. The result is placed into GPR rd. |
None | None |
| ORI rt, rs, immediate | To do a bitwise logical OR with a constant | rt = rs OR immediate The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical OR operation. The result is placed into GPR rt. |
None | None |
| SB rt, offset(base) | To store a byte to memory | memory[base+offset] = rt The least-significant 8-bit byte of GPR rt is stored in memory at the location specified by the effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address. |
None | None |
| SLL rd, rt, sa | To left-shift a word by a fixed number of bits | rd = rt << sa The contents of the low-order 32-bit word of GPR rt are shifted left, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa. |
None | None |
| SLLV rd, rt, rs | To left-shift a word by a variable number of bits | rd = rt << rs The contents of the low-order 32-bit word of GPR rt are shifted left, inserting zeros into the emptied bits; the result word is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs. |
None | None |
| SLT rd, rs, rt | To record the result of a less-than comparison | rd = (rs < rt) Compare the contents of GPR rs and GPR rt as signed integers and record the Boolean result of the comparison in GPR rd. If GPR rs is less than GPR rt, the result is 1 (true); otherwise, it is 0 (false). The arithmetic comparison does not cause an Integer Overflow exception. |
None | None |
| SLTI rt, rs, immediate | To record the result of a less-than comparison with a constant | rt = (rs < immediate) Compare the contents of GPR rs and the 16-bit signed immediate as signed integers and record the Boolean result of the comparison in GPR rt. If GPR rs is less than immediate, the result is 1 (true); otherwise, it is 0 (false). The arithmetic comparison does not cause an Integer Overflow exception. |
None | None |
| SLTIU rt, rs, immediate | To record the result of an unsigned less-than comparison with a constant | rt = (rs < immediate) Compare the contents of GPR rs and the sign-extended 16-bit immediate as unsigned integers and record the Boolean result of the comparison in GPR rt. If GPR rs is less than immediate, the result is 1 (true); otherwise, it is 0 (false). Because the 16-bit immediate is sign-extended before comparison, the instruction can represent the smallest or largest unsigned numbers. The representable values are at the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of the unsigned range. The arithmetic comparison does not cause an Integer Overflow exception. |
None | None |
| SLTU rd, rs, rt | To record the result of an unsigned less-than comparison | rd = (rs < rt) Compare the contents of GPR rs and GPR rt as unsigned integers and record the Boolean result of the comparison in GPR rd. If GPR rs is less than GPR rt, the result is 1 (true); otherwise, it is 0 (false). The arithmetic comparison does not cause an Integer Overflow exception. |
None | None |
| SRA rd, rt, sa | To execute an arithmetic right-shift of a word by a fixed number of bits | rd = rt >> sa (arithmetic) The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa. |
None | None |
| SRAV rd, rt, rs | To execute an arithmetic right-shift of a word by a variable number of bits | rd ¬ rt >> rs (arithmetic) The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs. |
None | None |
| SRL rd, rt, sa | To execute a logical right-shift of a word by a fixed number of bits | rd = rt >> sa (logical) The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa. |
None | None |
| SRLV rd, rt, rs | To execute a logical right-shift of a word by a variable number of bits | rd = rt >> rs (logical) The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs. |
None | None |
| SUB rd, rs, rt | To subtract 32-bit integers. If overflow occurs, then trap | rd = rs - rt The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs to produce a 32-bit result. If the subtraction results in 32-bit 2’s complement arithmetic overflow, then the destination register is not modified and an Integer Overflow exception occurs. If it does not overflow, the 32-bit result is placed into GPR rd. |
None | Integer Overflow |
| SUB.S fd, fs, ft | To subtract FP values | fd = fs - ft The value in FPR ft is subtracted from the value in FPR fs. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. SUB.PS subtracts the upper and lower halves of FPR fs and FPR ft independently, and ORs together any generated exceptional conditions. |
None | Inexact, Overflow, Underflow, Invalid Op, Unimplemented Op |
| SUBU rd, rs, rt | To subtract 32-bit integers | rd = rs - rt The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs and the 32-bit arithmetic result is and placed into GPR rd. No integer overflow exception occurs under any circumstances. |
None | None |
| SW rt, offset(base) | To store a word to memory | memory[base+offset] = rt The least-significant 32-bit word of register rt is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address. |
The effective address must be naturally-aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs. | TLB Refill, TLB Invalid, TLB Modified, Address Error, Watch |
| SWC1 ft, offset(base) | To store a word from an FPR to memory | memory[base+offset] = ft The low 32-bit word from FPR ft is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address. |
An Address Error exception occurs if EffectiveAddress1..0 != 0 (not word-aligned). | Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, TLB Modified, Address Error, Watch |
| SYSCALL | To cause a System Call exception | A system call exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. | None | System Call |
| XOR rd, rs, rt | To do a bitwise logical Exclusive OR | rd = rs XOR rt Combine the contents of GPR rs and GPR rt in a bitwise logical Exclusive OR operation and place the result into GPR rd. |
None | None |
| XORI rt, rs, immediate | To do a bitwise logical Exclusive OR with a constant | rt = rs XOR immediate Combine the contents of GPR rs and the 16-bit zero-extended immediate in a bitwise logical Exclusive OR operation and place the result into GPR rt. |
None | None |