4.3. Bus and Memory Transfers

4.3.1. BUS

If a computer has 16 registers, each holding 32 bits, how many wires are needed to connect every register to every other? (162) For a large number of wide registers, the wires could end up taking most of the space in the circuit.

A BUS is a single shared set of wires connecting all registers.

4.3.1.1. BUS with Multiplexers

Figure 4-3, bus system for 4 registers using multiplexers.

Bus, 4 8-bit registers connected for input and output. Use decoder/demux to drive load input on registers. Wire one MUX. Clock speed is limited by the propagation delay through the MUX and wires.

Only one register's contents can be on the bus for a given clock cycle. Which of the following are legal?

  • A ← B, C ← D
  • A ← C, D ← C
  • B ← D, B ← A

Book error: No R1 in the diagram.

	BUS ← C, A ← BUS
	

Can be written as:

	A ← C
	

Multiplexers must be driven to select register C t time units before the clock pulse that loads A, where t is the propagation delay of the multiplexers.

4.3.1.2. BUS with 3-state Buffers

3-state gates

3-state buffers can be used instead of multiplexers. A 3-state buffer is a combinational circuit that acts like a simple switch: It either passes the input signal to the output (C=1), or blocks the electrical current (C=0). The latter case is called high impedance state.

	I ------|>-------- O
		 |
	C -------+
	

3-state buffers can be used to connect or disconnect register outputs to/from the bus. A single decoder can control a large number of 3-state buffers. The outputs of the 3-state buffers can be tied directly together, provided that the circuit guarantees that all but one will be in high-impedance state at any given time. Using a decoder to control them guarantees this.

	
	

4.3.2. Memory Transfer

The internal bus connects only registers within the CPU, so how do we get data to and from memory?

The address register (AR) is used to select a memory address, and the data register (DR) is used to send and receive data. Both these registers are connected to the internal bus. DR is a bridge between the internal BUS and the memory data BUS.

Memory can also be connected directly to the internal BUS in theory.

Diagram showing connections to memory unit.

	M[AR] ← DR
	DR ← M[AR]
	

Hence, accessing memory outside the CPU requires at least two clock cycles. First we load AR with the desired memory address, and then transfer to or from DR. In most typical computer systems, memory transfers take many clock cycles, known as wait states. Solutions for reducing wait states are discussed in Chapter 12, Memory Organization.