5.2. Registers of the Basic Computer

5.2.1. Registers Overview

Book table 5-1:

Book figure 5-3:

  • PC/IP (Program Counter / Instruction Pointer, 12 bits) holds memory address of current/next instruction to be executed. Updated as part of the instruction cycle. (Usually incremented, but may be parallel loaded by jump/branch instructions.
  • IR (Instruction Register, 16 bits) holds the instruction code of the instruction currently executing. Outputs of this register are hardwired to specific logic in the control unit, which interprets the bits to generate control signals.
  • AR (Address Register, 12 bits) is used to interface with the memory unit. All memory-references are initiated by loading the memory address into AR.
  • AC (Accumulator, 16 bits) is used for all mathematical, logic, and shift operations operations except incrementing and clearing other registers (most have built-in increment and clear capability). It is the destination for all ALU operations, and a source for all dyadic (two-operand) operations.
  • DR (Data Register, 16 bits) is used to contain a second operand for dyadic operations such as add, sub, and, or.
  • TR (Temporary Register, 16 bits) is an extra register for storing data or addresses.
  • INPR and OUTR (Input and Output Registers, 8 bits) are used to communicate with the input and output devices. (The Basic Computer has one input device and one output device.)

5.2.2. Internal BUS Structure

Book figure 5-4:

  • Most registers have load, increment, and clear capabilities built-in. This eliminates the need to use the ALU or the BUS for increment and clear, and hence we can perform these operations on any register in parallel with other microoperations.
  • AR outputs are the memory address bus: they are directly connected to the address input of the memory unit.
  • AC and DR outputs hardwired into ALU. Hence, operands for dyadic operations such as add, sub, and, or must be in AC and DR.
  • Inputs of INPR are hardwired from the input device. We cannot transfer anything into INPR from the bus. Outputs of INPR are hardwired to ALU. We can only transfer INPR to AC.
  • Outputs of OUTR hardwired to the output device. We cannot transfer from OUTR to the bus.
  • Memory data inputs and outputs are connected directly to the internal bus.

Where to the outputs of the ALU go? What does this mean?


Where do the inputs of the ALU come from? What does this mean?


What happens when a 12-bit address is placed on the bus?


What is the sequence of microoperations for transferring M[IR(0-11)] to DR?

What is the sequence of microoperations for transferring DR to M[TR]?